The present invention relates to a phase change memory device and a method for manufacturing the same, and more particularly, to a phase change memory device in which a distance between a lower electrode and a ground line is increased so as to secure the sensing margin of a cell and a method for manufacturing the same.
In general, memory devices are largely divided into a volatile RAM (random access memory), which loses inputted information when power is interrupted and a non-volatile ROM (read-only memory), which can continuously maintain the stored state of inputted information even when power is interrupted. When considering the volatile RAM, a DRAM (dynamic RAM) and when considering SRAM (static RAM) can be mentioned, and as the non-volatile ROM, a flash memory device such as an EEPROM (electrically erasable and programmable ROM) can be mentioned.
As is well known in the art, while the DRAM is an excellent memory device, the DRAM must have high charge storing capacity, and to this end, since the surface area of an electrode must be increased, it is difficult to accomplish a high level of integration. Further, in the flash memory device, due to the fact that two gates are stacked on each other, a high operation voltage is required when compared to a source voltage. As a result a separate booster circuit is needed to form the voltage necessary for write and delete operations, making it difficult to accomplish a high level of integration.
To improve upon the current memory devices, researches have been active making an effort to develop a novel memory device that has a simple configuration and is capable of accomplishing a high level of integration while retaining the characteristics of the non-volatile memory device. A phase change memory device recently disclosed in the art is a product of this effort.
In the phase change memory device, a phase change, which occurs in a phase change layer interposed between a lower electrode and an upper electrode, from a crystalline state to an amorphous state is due to current flow between the lower electrode and the upper electrode. The information stored in a cell is recognized by the medium of a difference in resistance between the crystalline state and the amorphous state.
In detail, in the phase change memory device, a chalcogenide layer being a compound layer made of germanium (Ge), stibium (Sb) and tellurium (Te) is employed as a phase change layer. As a current is applied, the phase change layer undergoes a phase change by heat, that is, Joule heat, between the amorphous state and the crystalline state. Accordingly, in the phase change memory device, when considering the fact that the specific resistance of the phase change layer in the amorphous state is higher than the specific resistance of the phase change layer in the crystalline state, in a read mode, whether the information stored in a phase change cell has a logic value of ‘1’ or ‘0’ is determined by sensing the current flowing through the phase change layer.
FIG. 1 is a cross-sectional view illustrating a conventional phase change memory device.
Referring to FIG. 1, gates 110 are formed in the active region of a semiconductor substrate 100, which is delimited by an isolation structure (not shown). A source region 106S and a drain region 106D are formed in the surface of the semiconductor substrate 100 on both sides of the gate 110. A first oxide layer 112 and a second oxide layer 113 are formed on the overall surface of the substrate to cover the gates 110. A first metal plug 120 to come into contact with the drain region 106D and a second metal plug 121 to come into contact with the source region 106S are respectively formed in portions of the first oxide layer 112 which respectively correspond to a zone to be formed with a phase change cell and a zone to be formed with a line to be applied with a ground voltage (hereinafter, referred to as a ‘ground line (Vss line)’). In the second oxide layer 113, a lower electrode 130 is formed to come into contact with the first metal plug 120 in the phase change cell forming zone, and a ground line 171 is formed to come into contact with the second metal plug 121 in the ground line forming zone.
A third oxide layer 114 is formed on the second oxide layer 113 including the lower electrode 130 and the ground line 171. A lower electrode contact 140 having the shape of a plug is formed in the third oxide layer 114, and the lower electrode contact comes into contact with the lower electrode 130. A phase change layer 149 and an upper electrode 150 are sequentially stacked on the third oxide layer 114 to come into contact with the lower electrode contact 140. The unexplained reference numeral 105 designates a gate spacer.
In the conventional phase change memory device, as described above, the lower electrode 130 is formed in the drain region 106D to come into contact with the lower electrode contact 140, and the ground line 171 is formed in the source region 106S to apply the ground voltage. In this regard, if the distance “a” between the lower electrode 130 and the ground line 171 is decreased, due to the difference in voltage between the lower electrode 130 and the ground line 171, a leakage current is generated and the voltage of the ground line 171 increases.
The increase in the voltage of the ground line 171 causes a phenomenon in which when sensing the cells through bit lines connected to the upper electrodes 150, all cells are sensed as the amorphous state with high resistance. As a result, the distance ‘a’ between the lower electrode 130 and the ground line 171 serves as a substantial obstacle in decreasing the size of a unit cell in the conventional phase change memory device.